CMOS PLL Synthesizers: Analysis and Design

By Keliu Shu, Edgar Sanchez-Sinencio

This booklet provides either basics and the state-of-the-art of PLL synthesizer layout and research recommendations. an entire review of either system-level and circuit-level layout and research are coated. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is applied in 0.35m m CMOS. It encompasses a high-speed and powerful phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which take on velocity and integration bottlenecks of PLL synthesizer elegantly. This booklet is conceived as a PLL synthesizer guide for either academia researchers and layout engineers.

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