By Keliu Shu, Edgar Sanchez-Sinencio
This booklet provides either basics and the state-of-the-art of PLL synthesizer layout and research recommendations. an entire review of either system-level and circuit-level layout and research are coated. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is applied in 0.35m m CMOS. It encompasses a high-speed and powerful phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which take on velocity and integration bottlenecks of PLL synthesizer elegantly. This booklet is conceived as a PLL synthesizer guide for either academia researchers and layout engineers.
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Extra resources for CMOS PLL Synthesizers: Analysis and Design
Most sensible, Phase-locked Loops. 4th version, McGraw-Hill, 1999  B. Razavi, “A 900MHz/1. 8GHz CMOS transmitter for dual-band applications,” IEEE J. Solid-State Circuits, vol. 34, pp. 573-579, could 1999  A. Rofougaran, G. Chang, J. Rael, J. Chang, M. Rofougaran, P. Chang, M. Djafari, M. Ku, E. Roth, A. Abidi, and H. Samueli, “A single-chip 900-MHz spread-spectrum instant transceiver in CMOS – half I: structure and transmitter design,” IEEE J. Solid-State Circuits, vol. 33, pp. 515-534, Apr. 1998  S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, “Adaptive bandwidth DLLs and PLLs utilizing regulated offer CMOS buffers,” Symp. on VLSI Circuits Digest Technical Papers, Honolulu, hello, June 2000, pp. 124-127  A. J. Bishop, G. W. Roberts, and M. L. Blostein, “Adaptive section locked loop for video sign sampling,” in Proc. IEEE ISCAS’92, San Diego, CA, may perhaps 1992, pp. 1664-1667  G. Roh, Y. Lee, and B. Kim, “Optimum phase-acquisition strategy for charge-pump PLL,” IEEE J. Solid-State Circuits, vol. 32, pp. 729-740, Sept. 1997  J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE J. Solid-State Circuits, vol. 35, pp. 1137-1145, Aug. 2000  H. Shirahama, okay. Taniguchi, and okay. Nakashi, “A new very speedy pull-in PLL method with anti-pseudo-lock function,” in Proc. Symp. VLSI Circuits Dig. Tech. Papers, Kyoto, Japan, may perhaps 1993, pp. 75-76  C. Yang and S. Yuan, “Fast-switching frequency synthesizer with a discriminator-aided part detector,” IEEE J. Solid-State Circuits, vol. 35, pp. 1445-1452, Oct. 2000  Y. Tang, Y. Zhou, S. Bibyk, and M. Ismail, “A low-noise quickly settling PLL with prolonged loop bandwidth enhancement by means of new edition technique,” in Proc. IEEE ASIC/Soc Conf. , pp. 93-97, Sept. 2001  I. Hwang, S. track, and S. Kim, “A digitally managed phase-locked loop with a electronic phase-frequency detector for quick acquisition,” IEEE J. Solid-State Circuits, pp. 15741581, Oct. 2001  C. Lo and H. Luong, “A 1. 5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for instant applications,” IEEE J. Solid-State Circuits, vol. 37, pp. 459470, Apr. 2002  J. Hein and J. Scott, “z-domain version for discrete-time PLL’s,” IEEE Trans. Circuits Syst. vol. 35, pp. 1393 –1400, Nov. 1988  M. Paemel, “Analysis of a charge-pump PLL: a brand new model,” IEEE Trans. Commun. , vol. forty two, pp. 2490-2498, July 1994  C. Hedayat, A. Hachem Y. Leduc, and G. Benbassat, “High-level modeling utilized to the second-order charge-pump PLL circuit,” Texas tools Technical magazine, vol. 14, no. 2, pp. 99-107, Mar. -Apr. 1997  P. Larsson, “A simulator middle for charge-pump PLL,” IEEE Trans. Circuits Syst. II, vol. forty five, pp. 1323-1226, Sept. 1998  E. Liu and A. Sangiovanni-Vincentelli, “Behavioral representations for VCO and detectors in phase-locked systems,” in Proc. CICC, Boston, MA, might 1992, pp. 12. three. 14 3. PLL FREQUENCY SYNTHESIZER sixty seven  L. Wu, H. Jin, and W. Black, “Nonlinear behavioral modeling and simulation of phaselocked and delay-locked systems,” in Proc. CICC, Orlando, FL, might 2000, pp.